Publications



        Journal Publications

      1. A. Hosseinzadeh Namin, H.Wu, and M.Ahmadi, "Efficient Word Level Multiplier in Finite Field Using Redundant Representation", accepted for publishing by ACM Transactions on Embedded Computing Systems, 2011.

      2. A. Hosseinzadeh Namin, H.Wu, and M.Ahmadi, "High-Speed Architectures for Multiplication Using Reordered Normal Basis", accepted for publishing by IEEE Transactions on Computers, Oct. 2010.

      3. A. Hosseinzadeh Namin, K. Leboeuf, R. Muscedere, H. Wu, and M. Ahmadi, “High Speed Hardware Implementation of a Serial-In Parallel-Out Finite Field Multiplier Using Reordered Normal Basis”, IET Circuits, Devices & Systems, 4(2), 168-179, March 2010. (manuscript pdf)

      4. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “A High Speed Word Level Finite Field Multiplier in GF(2m) Using Redundant Representation”, IEEE Transactions on VLSI, 17(10), 1546-1550, 2009. (manuscript pdf)

      5. H. Wu, “Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields”, IEEE Transactions on Computers, 57(8), 1023-1031, August 2008.

      6. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “A New Finite Field Multiplier Using Redundant Representation”, IEEE Transactions on Computers, 57(5), 716-720, May 2008.

      7. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “Comb Architectures for Finite Field Multiplier”, IEEE Transactions on Computers, 56(7), 909-916, July 2007.

      8. B. Ansari, and H. Wu, “Efficient finite field processor for GF(2163) and its implementation”, International Journal of High Performance Systems Architecture, 1(2), 106-112, 2007.

      9. Z.Zheng, K.Tepe, and H.Wu, “Applying Unbalanced RSA to Authentication and Key Distribution in 802.11”, International Journal of Computer Science and Network Security, vol.5, pp.176-180, Oct. 2005.

      10. H.Wu, M.A.Hasan, I.F.Blake, and S.Gao, "Finite field multiplier using redundant representation," IEEE Trans. on Computers, vol.51, no.11, pp.1306-1316, 2002.

      11. H.Wu, "Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis", IEEE Trans. on Computers, vol 51, no.7, pp.750-758, July 2002.

      12. H.Wu, M.A.Hasan and I.F.Blake, "Low complexity parallel multiplier in F_q^n over F_q", IEEE Trans. on Circuits and Systems, Part I, vol.49, no.7, pp.1009-1013, July 2002.

      13. H.Wu, "Montgomery multiplier and squarer for a class of finite fields", IEEE Trans. on Computers, vol.51, no.5, pp.521-529, May 2002.

      14. H.Wu and M.A.Hasan, "Efficient exponentiation using weakly dual basis", IEEE Trans. on VLSI Systems, vol.9, no 6, pp.874-879, Dec. 2001.

      15. H.Wu and M.A.Hasan, "Closed-form expression for the average weight of signed-digit representations", IEEE Trans. on Computers, vol.48, no 8, pp.848-851, August 1999.

      16. H.Wu, M.A.Hasan and I.F.Blake, "Low complexity weakly dual basis bit-parallel multiplier over finite fields", IEEE Trans. on Computers, vol.47, no.11, pp.1223-1234, Nov. 1998.

      17. H.Wu and M.A.Hasan, "Low complexity bit-parallel finite field multiplier for a class of fields", IEEE Trans. on Computers, vol.47, no.8, pp.883-887,  Aug. 1998.

      18. H.Wu and M.A.Hasan, "Efficient exponentiation of a primitive root in GF(2^m)", IEEE Trans. on Computers, vol.46, no.2, pp.162-172, Feb. 1997.

        Selected Conference Publications

      1. K. Leboeuf, A. Hosseinzadeh Namin, R. Muscedere, H. Wu, and M. Ahmadi, “Efficient Hardware Implementation of the Hyperbolic Tangent Sigmoid Function”,  The 2009 IEEE International Symposium on Circuits and Systems (ISCAS09), 2117-2120, 2009.

      2. K. Leboeuf, A. Hosseinzadeh Namin, R. Muscedere, H. Wu, and M. Ahmadi, “High Speed VLSI Implementation of the Hyperbolic Tangent Sigmoid Function”, Proceedings of the 2008 International Conference on Convergence and hybrid Information Technology (ICCIT08). 1070-1073, December 2008. (manuscript)

      3. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “A High Speed Word Level Finite Field Multiplier Using Reordered Normal Basis”, Proceedings of the 2008 IEEE International Symposium on Circuits and Systems (ISCAS08), 3278-3281, May 2008.(manuscript)

      4. B. Ansari, H. Wu, “Efficient Finite Field Processor for GF(2^163) and its VLSI Implementation”, ITNG 2007, 1021-1026, July 2007.(manuscript)

      5. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “A Bit-Serial Word-Parallel Finite Field Multiplier Using Redundant Basis in F(2m)”, Proceedings of IASTED International Conference on Communication Systems and Networks (AsiaCSN), 171-176, April 2007.(manuscript)

      6. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi jid, “A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields”, Proceedings of the 13th IEEE International Conference on Electronics, Circuits, and Systems (ICECS06), 502-505, December 2006.(manuscript)

      7. H. Wu, “Low Complexity Bit-Parallel Finite Field Polynomial Basis Multiplier for A Class of Pentanomials”, Proceedings of 2006 International Conference on Communications, Circuits and Systems (ICCCS06), vol. VI, pp. 2565-2568, June 2006.(manuscript)

      8. A. Hosseinzadeh Namin, H. Wu, and M. Ahmadi, “A Serial-In Parallel-Out Multiplier Using Redundant Representation For A Class of Finite Fields”, Proceedings of 40th Asilomar Conference on Signals, Systems and Computers (ACSSC), 1702-1705, October 2006.(manuscript)

      9. K.Biswas, H.Wu, and M.Ahmadi, “Fixed-Width Multi-Level Recursive Multiplier”, Proceedings of 40th Asilomar Conference on Signals, Systems and Computers (ACSSC), 935-938, October 2006.(manuscript)

      10. H.Wu, “Efficient Implementation of DFT over GF(q^m)”, Proceedings of 40th Asilomar Conference on Signals, Systems and Computers (ACSSC), 1180-1182, October 2006.(manuscript)

      11. A.Hosseinzadah Namin, H.Wu, and M.Ahmadi, “High Speed Bit-Parallel Word-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation”, The 39th Asilomar Conference on Signals, Systems and Computers (ACSSC), Monterey, CA, the USA. 1338-1341, Nov. 2005.(manuscript)

      12. M.Pedram, K.Biswas, H.Wu, and M.Ahmadi, “Truncation Schemes for Recursive Multipliers”, The 39th Asilomar Conference on Signals, Systems and Computers, Monterey (ACSSC), CA, USA. 1177-1180, Nov. 2005.(manuscript)

      13. W.Dai, H.Kwan, and H.Wu, “IP Protection for FPGA Implementation of DSP Algorithms”, The 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, OH, the USA. pp.273, Aug. 2005.(manuscript)

      14. B.Ansari, and H.Wu, “Parallel Computation of Scalar Multiplication for Elliptic Curve Cryptosystems”, The Ninth Canadian Workshop on Information Theory (CWIT), Montreal, PQ, Canada. 379-382, June 2005.(manuscript)

      15. W.Tang, H.Wu, and M.Ahmadi, “VLSI Implementation of Bit-Parallel Word-Serial in GF(2^233)”, Proceedings on IEEE-NEWCAS Conference, Quebec City, PQ, Canada, pp.290-293, June 2005.(manuscript)

      16. Z.Zheng, K.Tepe, and H.Wu, “Applying Unbalanced RSA to Authentication and Key Distribution in 802.11”, The Ninth Canadian Workshop on Information Theory(CWIT), pp. 280-283, June. 2005.(manuscript)

      17. B.Ansari, and H.Wu, “Parallel Scalar Multiplication for Elliptic Curve Cryptosystems”, Proceedings of International Conference on Communications, Circuits and Systems (ICCCAS 2005), Hong Kong. 71-73, May 2005.(manuscript)

      18. G.Gong, L.Harn, and H.Wu, "The GH Public-key Cryptosystem," in the Proceedings of Selected Areas in Cryptography-SAC 2001, also in LNCS 2259, pp.284-300, Springer-Verlag, 2001.(manuscript)

      19. H.Wu, "On complexity of polynomial basis squaring in GF(2^m)," in the Proceedings of Selected Areas in Cryptography-SAC 2000, also in LNCS 2012, pp.118-129, Springer-Verlag, 2001.(manuscript)

      20. H.Wu, "Montgomery Multipier and Squarer in GF(2^m)," in the Proceedings of Cryptographic Hardware and Embedded Systems-CHES 2000, also in LNCS 1965, pp.264-276, Springer-Verlag, 2000.

      21. H.Wu, "Low complexity finite field arithmetic using polynomial basis," in the Proceedings of Cryptographic Hardware and Embedded Systems- CHES 1999, also in LNCS 1771, pp.357-371, Springer-Verlag, 2000.

      22. H.Wu, M.A.Hasan and I.F.Blake, "Highly regular architectures for finite field Computation using redundant basis," in the Proceedings of Cryptographic Hardware and Embedded Systems-CHES 1999, also in LNCS 1771, pp.264-276, Springer-Verlag,2000.

      23. H.Wu, M.A.Hasan and I.F.Blake, "Efficient computation of point multiples on elliptic curves," in the Proceedings of 1998 IEEE International Symposium on Information Theory, pp.49, Cambridge, MA, Aug. 1998.

      24. H.Wu and M.A.Hasan, "Efficient realization of a class of sequence generators," in the Proc. IEEE Paci. Rim Conf. Comm., Comput. and Signal Process., pp.511-514, Victoria, BC, Aug. 1997.

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